• Added support for new TMI features.
  
• HICUM/L0 version 2.1.0 has been added to ADS.
  
• Angelov GaN model has been updated to version 3.1.
  
• Added a new built-in function wsp_zo_renorm_s() to recompute the S-parameters given the input and output impedances.
  

• Improved Description step-size autoscaling and changed calculation to be a manual process within Description Options.
  
• Improved performance for the ads-dataset and PathWave Data Tools Python libraries for ADS dataset reading and writing.
  
• (Beta Release) Several new capabilities have been added to DDS Python APIs:
  

• A new font, Roboto, has been added to the product. Roboto will become the default font, replacing the deprecated Arial For CAE, in the upcoming releases.
  
• AEL function, de_unarchive_file(), has been added for unarchiving workspaces, libraries and files.
  
• Obsolescence announcement: The menus and associated utilities for converting legacy prj/dsn to OpenAccess workspace have been removed.
  
• (Beta Feature) The Python console, available and accessible from a top-level 'Python' menu, can be used to control workflow, modify workspaces, automate tasks, and customize the user interface via Python APIs.
  

• The Move annotation command has been improved to handle instance-based pins without showing double ghost images.
  
• The PCB stacked Via, which is made up of a collection of via rules, can now be edited as a single object.
  
• A padstack specification change in PCB Via definition is automatically reflected in PCB Via instances.
  
• The PCB stacked via references can be updated using the ADS main window File > Update References... dialog box. For more details, refer Update References.
  
• The Ground Planes editing options can now be fully accessed from the Properties window. Additional ground plane properties are now editable: rounded clearance, remove islands, thermal relief, degassing; degas toggle and degas edit dialog are also accessible from the Properties window. Multiple ground planes can be selected and edited via the Properties window.
  
• A new display option, Display PCB Via Layer Span, is available in the Display tab of the Layout > Options > Preferences dialog box for enabling visualizing the layer span for all PCB via instances in layout. For more details, refer Display Options.
  
• The selection filter in the Layout > Options > Preferences > Select tab has been augmented with new options, "OA Vias" and "PCB Vias", to differentiate the selection between OpenAccess vias and PCB vias. Note that PCB vias will not be highlighted as Components.
  
• Design Differences has been enhanced to allow a user to compare and update net names between layout and schematic if the Keep Net Names From Schematic/Layout option is enabled. If this setting is enabled, the schematics generated from a layout will be placed with the same nets as their layout counterparts. This option can be accessed through the Design Differences window by clicking on the blue gear icon.
  
• Updated layout's Assign Nets to Layout... command, available via Tools > Assign Nets to Layout menu in the Layout window, to only assign nets to shapes whose layers have a layer binding or have the process role "Conductor" or "Conductor Via".
  
• Path/Trace objects can now retain custom properties when edited.
  
• Exiting ADS will no longer prompt for confirmation unless there are modified files open or active simulations running.
  

• AEL function, db_oversize_ex(), added for oversizing selected objects.
  
• AEL function, de_set_instance_mirror_ex(), added for setting the mirror preference for instance to be placed in the design.
  
• New AEL functions have been added for querying attributes of a given stacked PCB via instance:
  

• AEL function, db_stack_via_rule_exists(), added for checking if a given stacked via rule exists.
  
• AEL function, db_create_fig_group_from_selected(), added for creating a group from the selected object(s) in the design.
  
• AEL function, dxf_import_design(), now supports arbitrary view names for ADS top-level designs.
  
• AEL functions, db_activate_instance(), db_deactivate_instance() and db_deactivate_and_short_instance(), added for activating/deactivating instances.
  
• Added new AEL functions:
  

• ABL import is enhanced to allow the BOM attribute and the instance prefix value to be specified for item definition creation.
  
• A deprecation warning message is added to the ABL import log when the ABL import AEL API is invoked with the deprecated argument of option file path name in its call.
  
• Recognition of the coordinate format, FILE_FORMAT, is improved in Gerber Import to support the Altium Designer format attribute.
  
• DXF/DWG export now supports a new hole format option, "Holes as slices", that preserves arcs in the output DXF/DWG file. For more details, refer Export DXF/DWG Options.
  
• DXF Import: hatches can be optionally converted to polygons with holes. For more details, refer DXF/DWG Translator.
  
• The Gerber import log no longer includes a warning message related to the Mirror Image (MI) command when mirror imaging is disabled (MIA0B0).
  

• The ICT import in the LTD substrate editor now supports thickness bias in addition to the already supported width and resistivity bias.
  
• Area pins with holes are now supported.
  

• When you rerun an analysis, either a single simulation or a parameter sweep, and the simulation inputs have not changed, the system does not rerun the simulation but reuses the previous results.
  
• Fine tuned the capability to create an analysis from an EM Setup view. Where applicable, analysis settings are initialized based on the EM Setup view findings. In addition, a method is added to the Python API that performs the same action.
  

• USB4V2 Compliance solution has been developed to support compliance tests for USB4.0.
  
• Chiplet PHY Designer - Support Design Exploration with HTML report.
  
• AMI Modeler - AMI sub-model is now supported.
  
• FoM (Figure of Merit) Compliance in the S-Parameter Toolkit has been implemented.
  

• ODB++ import now supports negative layers.
  
• The Component Model Library Tool table view now has an auto-complete cell name for the Murata library.
  
• Component Model Library Tool supports vendor PDK databases such as Murata, Samsung, TDK, Vishay, etc.
  
• Component Model Library Tool now has an import button to allow the user to specify a specific SQLite database for the model map.
  
• PIPro AC Analysis frequency plan can now be resorted in order of frequency.
  
• PIPro AC frequency plans can now be imported/exported in an xml format for ease of reuse.
  
• Field evaluation python API for PPR.
  
• The Component Model Library Tool can be used to create a murata_defaults cell that allows Murata library models or other vendor libraries to be included as LibCell models in SIPro/PIPro simulations.
  
• ODB++ import now supports negative layers
  

• LVS performance is improved for conductive shapes with metal slotting (polygons with many small holes).
  
• LVS dialog configures the column width to show the full text.
  
• LVS dialog selects the IC library rule location after pushing into an IC from a multi-technology design.
  

• Fixed an issue of loading older .dds files with invalid color indexes.
  
• Changed ads-dataset dataframe to support both Index and MultiIndex to better support writing dataframes with one independent variable to a dataset.
  

• In Design Cloud Lite mode under Local Queue option, canceling a simulation will now cancel the job cleanly rather than showing error.
  
• Fixed an issue where scalar measurement equation values may be concatenated into a list.
  
• Fixed circuit simulation results installation when simulation directory is a symlink across different NFS mount.
  

• Fixed an issue with ETH results installation when the source and destination directories are owned by different users.
  
• Fixed a dataset merge issue occurring when ETH simulation is run with parallel jobs = 2.
  

• Fixed an issue where an external file is contained within the shared root but the user still adds the file path in the upload file section in design cloud simulation settings.
  
• Fixed an issue for the installation of the bit pattern file generated by the WCBP generator.
  

• Fixed a bug where plane degassing did not properly avoid all the vias, particularly in the case where vias were placed via array instance.
  
• (Beta Release of Python APIs) Fixed a bug where computed parameters did not always take effect on an instance when modifying them in a Python-implemented parameter modified callback, such as the Area parameter when dragging a vertex of a polygon component in the drag handles example provided with ADS.
  

• Fixed a bug in the ITF import in the LTD substrate editor to properly deal with mask coloring.
  
• Fixed a bug in the LTD substrate editor to properly update the metal bias tables when changing the unit.
  
• Fixed a bug to correctly set the number of threads for the child jobs during a parallel frequency sweep.
  
• Fixed a bug that prohibited Momentum to run more than 64 threads.
  

• Improved error reporting to help understand why RFPro cannot open a design.
  
• Fixed a bug in the port creation for FEM Generation 2 in case port pins touch or overlap.
  

• Differential lines now can have coaxial ports under the condition that the ports of the positive and negative line do not overlap.
  
• Automatic port creation does not create virtual pin on nearest ground.
  

• ODB++ import now defaults to lower case and detailed (previously called legacy) cell names.
  
• Minor bug fixes for improved ODB++ import of paths and traces.
  
• Taiyo Yuden PDK for capacitors.
  
• PIPro DC via resistance now adjusts for meshed cross section vs. physical cross-section area.
  

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